MOSFET (metal-oxide-semiconductor field effect transistor) devices have many electrical applications including use in RF/microwave amplifiers. In such applications, the gate to drain feedback capacitance must be minimized in order to maximize RF gain and minimize signal distortion. In a silicon power MOSFET, the gate electrode provides turn-on and turn-off control upon the application of an appropriate gate bias.
Conventional technologies for reducing the gate to drain capacitance Cgd in a DMOS device are still confronted with technical limitations and difficulties. Specially, trenched DMOS devices are configured with trenched gates wherein large capacitance (Cgd) between gate and drain limits the device switching speed. The capacitance is mainly generated from the electrical field coupling between the bottom of the trenched gate and the drain. In order to reduce the gate to drain capacitance, an improved Shielded Gate Trench (SGT) structure is introduces at the bottom of the trenched gate to shield the trenched gate from the drain.
U.S. Pat. Nos. 5,126,807 and 5,998,833 illustrate examples of shielded gate trench (SGT) MOSFET as a promising solution in high speed switching applications with the SGT function as a floating gate in the lower part of the trench or fix to a source voltage. However, a challenge of the processes disclosed in the above-mentioned references is to control the depth of the floating gate in order to avoid the malfunction of the MOSFET. Control of etch depth is particularly important, e.g. when etching back polysilicon to the middle of the gate trench because this is not an end point etch. As the feature sizes continue to shrink floating gate etch back control becomes a more challenging and important task.
A common prior art technique for controlling etch depth, referred to herein as time control, involves control of the etch duration. In this technique an etch rate is determined and the etch depth may be calculated by timing the etch process and multiplying the etch rate by the etch duration. Unfortunately, the etching rate for polysilicon highly depends on numerous factors including, e.g., polysilicon grain size, doping, trench size and overall loading effect. Thus, the etch rate for polysilicon can be difficult to determine and the actual etch back depth is uncertain. This makes it difficult to improve the device manufacturing as no data related to the etch back depth except the etch back time is available to correlate the device performance with the etch back depth.
It is within this context that embodiments of the present invention arise.